The present invention relates generally to static data storage a in particular the present invention relates to a non-volatile flash memory device.
A flash memory device is a non-volatile memory, derived from erasable programmable read-only memory (EPROM) and electrically-erasable programmable read-only memory (EEPROM). Flash memory is being increasingly used to store execution codes and data in portable electronic products, such as computer systems.
A typical flash memory comprises a memory array having a large number of memory cells arranged in blocks. Each of the memory cells is fabricated as a field-effect transistor having a control gate and a floating gate. The floating gate is capable of holding a charge, and is separated, by a layer of thin oxide, from source and drain regions contained in a substrate. Each of the memory cells can be electrically programmed (charged) by injecting electrons from the drain region through the oxide layer onto the floating gate. The charge can be removed from the floating gate by tunneling the electrons to the source through the oxide layer during an erase operation. Thus the data in a memory cell is determined by the presence or absence of a charge on the floating gate.
Flash memories have a typical operating voltage in the range of about 1.8 to 5 volts. A high voltage, however, is usually required for programming and erase operations in a flash memory. This high voltage (Vpp) is in the range of 10 to 13 volts, but can be higher. During a programming operation, electrons are injected onto the floating gate by applying the high voltage (Vpp) to the control gate and about one-half Vpp to the drain region while the source region is grounded. Electron tunneling from the floating gate during an erase operation is accomplished by applying Vpp to the source region, connecting the control gate to ground potential and leaving the drain region electrically unconnected or floating. Alternately, a large negative voltage could be applied to the gate and a higher voltage applied to the source to perform a negative gate erase operation.
The construction and operation of a basic stacked floating gate memory cell is described with reference to FIGS. 1A, 1B and 1C. FIG. 1A is a cross-sectional view of a typical floating gate memory cell used in flash memories. Memory cell 100 comprises a source region 102 and a drain region 104. Source 102 and drain 104 are constructed from N+type regions formed in a P-type semiconductor substrate 106. Source 102 and drain 104 are separated by a channel region 108. Memory cell 100 further includes a floating gate 110 formed by a first polysilicon (poly) layer, and a control gate 114 formed by a second poly layer. Floating gate 110 is isolated from control gate 114 by an interpoly dielectric layer 112 and from channel region 108 by a thin gate oxide layer 116. The source region 102 has a deeper junction than the drain region 104 for improving erase operations.
FIG. 1B is the memory cell of FIG. 1A during a programming operation. To program the memory cell to store a charge, a positive programming voltage of about 12 volts is applied to control gate 114. This positive programming voltage attracts electrons 120 from P-type substrate 106 and causes them to accumulate toward the surface of channel region 108. The drain 104 voltage is increased to about 5 volts, and source 102 is connected to ground. As the drain-to-source voltage increases, electrons 120 begin to flow from source 102 to drain 104 via channel region 108. Electrons 120 acquire substantially large kinetic energy and are referred to as hot electrons.
The voltage difference between control gate 114 and drain 104 creates an electric field through oxide layer 116, this electric field attracts the hot electrons and accelerates them towards floating gate 110. Floating gate 110 starts to trap and accumulate the hot electrons, beginning the charging process. As the charge on the floating gate increases, the electric field through oxide layer 116 decreases and eventually loses it capability of attracting any more of the hot electrons. At this point, floating gate 110 is fully charged. The charged floating gate 110 raises the memory cell""s threshold voltage (Vt) above logic 1 voltage. Thus, when control gate 114 is brought to a logic 1 (H) during a read operation, the memory cell will barely turn on. As known to those skilled in the art, sense amplifiers are typically used in a memory to detect and amplify the state of the memory cell.
FIG. 1C is the memory cell of FIG. 1B during an erase operation. The memory cell is erased by discharging the floating gate. To erase the memory cell, a positive voltage of about 12 volts is applied to source 102 while control gate 114 is connected to ground and drain 104 is left unconnected, electrically floating. Alternatively, a negative voltage, such as xe2x88x9210 volts, can be applied to the control gate while the source is coupled to 5 volts. With a higher relative voltage at source 102, negatively-charged hot electrons 120 are attracted and tunneled to source 102 through the thin gate oxide layer 116. The tunneling is stopped when the floating gate is discharged. To avoid over erasure, the voltage applied to the source is typically applied in short pulses having equal duration and magnitude. That is, if one memory cell in a block does not fully erase during an erase operation, it is preferred to use short erase pulses to erase the memory block. The short erase pulse is an attempt to prevent over erasing memory cells in the block that are already erased. The lack of negative charge on floating gate 110 returns the memory cell""s threshold voltage below logic 1 voltage. Thus, when a voltage on control gate 114 is brought to a logic 1 during a read operation, the memory cell will turn on.
FIG. 2 illustrates a portion of a memory array arranged in rows and columns. A non-volatile memory cell is located at an intersection of each row and column. Errors can be experienced during read operations when one, or more, of the memory cells have been over-erased. That is, an error can be experienced while reading memory cell 200 if memory cell 202 is over-erased. This error is due primarily to the fact that memory cells 200 and 202 are coupled to the same column during read operations. During the read operation, Row 1 has a signal of approximately five volts, and the source line 201 shared by a block of memory cells is coupled to ground. A state of the memory cell 200 is determined by the current flow on Column1. If memory cell 202 is over erased, such that its threshold voltage is below the threshold voltage of an un-charged memory cell, the current flow on Column1 is influenced by memory cell 202. Such that, memory cell 202 conducts additional current because it has a threshold voltage in the range of xe2x88x921 to 0.5 volts.
In an effort to address errors resulting from over erased non-volatile memory cells, sophisticated algorithms are performed to over erase cells and then perform a heal operation to return memory cell threshold voltages to an acceptable range. In addition, unselected memory row lines can be forced to a negative voltage during read operations to force unselected cells to remain off. Both approaches require additional undesirable operating steps.
A split gate memory cell 210, illustrated in FIGS. 3A and 3B, helps address errors created by over erased memory cells. The split gate memory cell 210 includes a floating gate 212 located on an insulating layer 214. The floating gate is separated from a control gate 216 by another insulating layer 213. The control gate is fabricated in a split fashion (216 and 218), such that a traditional MOS transistor 230 is fabricated in parallel with the floating gate transistor 232. These transistors share a common drain region 220 and source region 222. If the floating gate memory cell is over erased, a current path through the series coupled transistors is not formed while the gate voltage is coupled to ground. While this memory cell helps eliminate errors due to over erased cells, it has a large cell size and substantially increases a layout of the memory array.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a non-volatile memory device which prevents errors due to over erased memory cells without requiring sophisticated operating algorithms, or substantial increases in integrated circuit die area.
The above mentioned problems with non-volatile memory devices and other problems are addressed by the present invention and which will be understood by reading and studying the following specification. A split source line architecture is described which isolates unselected memory cells to prevent read errors.
In particular, the present invention describes a non-volatile memory device comprising an array of non-volatile memory cells arranged in rows and columns. The non-volatile memory cells have a control gate coupled to receive one of a plurality of row line signals, a drain region and a source region. A first source line is coupled to the source region of the non-volatile memory cells, and a plurality of isolation transistors are coupled to the first source line and a second source line. The plurality of isolation transistors are adapted to selectively couple the first source line to the second source line in response to one of the plurality of row line signals.
In another embodiment, a processing system comprises a processor, and a flash memory device coupled to the processor. The flash memory comprises an array of floating gate memory cells arranged in rows and columns. The floating gate memory cells each have a control gate coupled to receive one of a plurality of row line signals, a drain region coupled to a column line, and a source region coupled to a first source line. A plurality of isolation transistors are coupled to the first source line and a second source line. Each one of the plurality of isolation transistors has a gate coupled to receive one of the plurality of row line signals such that the first source line and the second source line are electrically coupled in response to one of the plurality of row line signals and unselected memory cells are isolated from the second source line.
A method is described for reducing read errors in a memory device resulting from over erased non-volatile memory cells. The method comprises initiating a read operation in the memory device, and activating a row line signal to select a row of memory cells having a source region coupled to a first source line. A first isolation transistor is activated in response to the activated row line signal to electrically couple the first source line to a second source line, and a second isolation transistor is de-activated in response to a de-activated row line signal.